Electronic firing circuit

ABSTRACT

In an electronic firing circuit including a firing capacitor the charge on the firing capacitor is used as a control signal to isolate a firing thyristor from an erroneous triggering signal.

United States Patent [191 Fillmore et al.

[451 Jan. 29, 1974 ELECTRONIC FIRING CIRCUIT [75] Inventors: Richard Plumb Fillmore, Plainfield;

Robert Charles Heuner, Bound Brook, both of NJ.

[73] Assignee: RCA Corporation, New York, NY.

[22] Filed: July 18, 1972 [21] Appl. No.: 272,956

[52] US. Cl. l02/70.2 R, 102/70.2 P, 320/1 [51] Int. Cl F42c 11/06, F42c 11/00 [58] Field of Search 102/702; 320/1 [56] References Cited UNITED STATES PATENTS 3,624,481 11/1971 Macharg 320/1 Lesher 320/1 Flieder 320/] Primary Examiner-Benjamin A. Borchelt Assistant Examiner-Thomas H. Webb [5 7] ABSTRACT In an electronic firing circuit including a firing capacitor the charge on the firing capacitor is used as a control signal to isolate a firing thyristor from an erroneous triggering signal.

15 Claims, 1 Drawing Figure PAHENIEUJA-29 19M I 1 59 i l l q arm ELECTRONIC FIRING CIRCUIT The invention herein described was made in the course of or under a contract or subcontract thereun der with the Department of the Army.

The present invention relates to electronic firing circuits and, particularly, to an electronic firing circuit which combines MOS and bipolar technology to provide timing functions to a monolithic SCR output device.

In certain types of firing control systems hitherto known or used in connection with ordnance devices it is the practice to employ an energy storage device which is adapted to render the firing circuit thereof effective when a signal corresponding to a predetermined change in a physical variable is received. For example, it might be desirable to provide an ordnance system for use with anti-tank or anti-personnel mines where the mines are manually armed at the time of implantation and set to detonate as a result of subsequent physical disturbance. Alternatively, it might be desirable to provide an ordnance system for use with a marine mine which may be air lifted to a desired geographic location and dropped into the water whereupon the energy storage device would be charged from an internal power supply activated as a result thereof. Thereafter, the mine could be detonated in response to the approach of a metal object, such as an enemy vessel, whose presence would be sensed by an appropriate sensing system and which would result in the generation of a firing signal. A critical prerequisite of any such system is to insure against premature triggering of the firing circuit which might prematurely detonate the mine or preclude subsequent detonation at the desired time.

In an electronic firing circuit for controlling the detonation of an explosive charge, in accordance with a typical embodiment of the present invention, the charge on a firing capacitor is used as a control signal to isolate a firing thyristor from an erroneous triggering signal.

The present invention will be more fully understood by reference to the following detailed description in conjunction with the accompanying drawing which is illustrative of an electronic firing circuit in accordance with the present invention.

Low power consumption, high reliability, miniaturization, and weight advantages have made it desirable to apply modern solid state technology to the problems of ordnance control circuits. The circuit depicted in the drawing is illustrative of an electronic firing circuit which combines MOS and bipolar technology on a single monolithic substrate. To obtain an understanding of the basic principles involved in the design and application of monolithic circuits containing p-channel and nchannel MOS transistors as used herein, the reader is referred to the RCA COS/MOS Integrated Circuits Manual Technical Series CMS-270, published in 1971 by RCA Corporation.

Turning to a description of the circuit shown in the drawing, the commonly connected gate electrodes of a complementary symmetry metal-oxide-semiconductor (COS/MOS) inverter comprising ap-channel 22 and an n-channel 24 enhancement-type MOS transistor serve as the input terminal of an output stage coupled to circuit logic means 10. With a signal corresponding to a logical zero applied to the input of inverter circuit 20, the gate-to-source voltage of the p-channel device 22 is equal to the supply voltage (V,,,,) and the pchannel device 22 is in a conducting state. Under these conditions there is a low impedance path from the output of inverter 20 (taken from the commonly connected drain electrodes) to V and a high impedance path to ground resulting in an output signal which approaches V With a signal corresponding to a logical one applied to the input of inverter 20 the situation is reversed; i.e. the p-channel transistor 22 is cut off, the n-channel transistor 24 is switched on, and the output terminal of inverter 20 is clamped to ground.

The output of COS/MOS inverter 20 is connected to the gate electrode (g) of an SCR device 30 (circumscribed in phantom) through the :source-to-drain path of a single n-channel MOS transistor transmission gate 26. The SCR 350 is a composite llateral-PNP/vertical- NPN bipolar transistor, fabricated by means of standard COS/MOS diffusion profiles, and formed on the same monolithic substrate with the MOS devices. The gate electrode of transistor 26 is connected to the anode (a) of SCR 30. A detonator 50, adapted to fire an explosive charge, is connected between the cathode (c) of SCR 30 and ground; a shunting resistor 32 is similarly connected between the gate (g) of SCR 30 and ground.

A storage capacitor 40 is connected between the anode (a) of SCR 30 and ground. A charging circuit for capacitor 40 is provided via the gate-to-source path of a p-channel transistor 28 which is: connected between the anode (a) of SCR 30 and V the conduction of transistor 28 being controlled by the application of a signal (V,,,,,,) to its gate electrode in a manner to be hereinafter described.

Circuit operation is predicted on. the theory that storage capacitor 40, which is initially uncharged, will charge at the appropriate time thereby arming the circuit. In the case of an air-dropped land mine, for example, capacitor charging may occur as a result of initial impact with the ground. Thereafter, as a result of subsequent vehicle disturbance such as contact with a tank or similar vehicle, a logic signal will be generated by the logic circuit 10 to the input of the COS/MOS inverter 20 resulting in the delivery of a triggering signal to the gate electrode (g) of SCR 30 via transistor 26 which will result in the discharge of capacitor 40 via the anode-to-cathode path of SCR 30 causing the detonator 50 to fire.

More specifically, at a first point in time (for example, when the mine makes initial impact with the ground as discussed supra) an arming signal (V,,,,,,) is provided to the gate electrode of p-channel transistor 28 which renders the device conductive thereby charging capacitor 40 as a function of V Ideally, at such point in time the output of the COS/MOS inverter 20 is clamped to ground thereby precluding the availability of a triggering signal for SCR 30. Sometimes, however, an erroneous signal may be transmitted at such point in time which would, in the absence of transistors 26, provide a triggering signal to the gate electrode (g) of SCR 30. This may be as a result of diffusion coupling or transient switching error. In the disclosed circuit such a situation is prevented by transistor 26 which is precluded from becoming conductive until capacitor 40 has been charged to a predetermined potential sufficient to forward bias the gate electrode thereof. In addition, because the signal appearing at the gate electrode of transistor 26 via the source-to-drain path of transistor 28 is insufficient to overcome the threshold value of transistor 26, transistor 28 can be permitted to remain in a conducting state to replenish any charge which has leaked off capacitor 40.

Thereafter, at a subsequent point in time (for example, when the mine is physically distrubed by a tank as discussed supra) logic circuit means cause a logical zero to be generated and applied to the input of COS/MOS inverter causing transistor 22 to become conductive. The charge on capacitor 40 at such subsequent point in time is sufficient to bias transistor 26 into conduction and a triggering signal is provided to the gate (g) of SCR 30 via the source-to-drain path of transistor 26 which signal will trigger SCR 30 into condution. When SCR 30 is triggered into conduction capacitor 40 will discharge via the anode-to-cathode path of the SCR causing the detonator to fire. Alternatively, a firing signal may be generated by logic means 10 as a result of the lapse of a predetermined period of time or other preprogrammable condition.

The circuit depicted in the drawing and described herein has been successfully constructed and tested using a 120 microfarad capacitor (40), a 20,000 ohm shunting resistor (32), and a supply voltage (V of approximately 67 volts.

Accordingly, an electronic firing circuit which combines MOS and bipolar technology has been disclosed wherein the charge on the firing capacitor is used as a control signal to isolate a monolithic SCR from an erroneous triggering signal and wherein the energy stored in said capacitor is used as a source of load current to fire a detonator.

What is claimed is:

1. An electronic firing circuit comprising:

a silicon controlled rectifier having anode, cathode,

and gate electrodes;

detonating means adapted to fire an explosive charge, said detonating means being connected in series circuit with the anode-to-cathode path of said rectifier;

a firing capacitor connected in circuit with said series combination, said capacitor being adapted to provide a firing current to said detonating means via said anode-to-cathode path; 7

a charging circuit including a first transistor connected in circuit with said capacitor, said charging circuit being adapted to charge said capacitor to a desired potential upon the application of an arming signal to the control electrode of said transistor;

an inverter circuit comprising a complementary pair of transistors and having an input terminal and an output terminal, said inverter circuit exhibiting a first conduction state in response to a given logic signal at its input terminal and a second conduction state in the absence of said given logic signal;

logic means for generating said given logic signal, said logic means being connected to said inverter input; and

triggering means including a further transistor connected in circuit with said inverter output terminal, said rectifier gate electrode and said capacitor;

said triggering means being adapted to preclude the application of a triggering signal to said rectifier gate when the charge on said capacitor is below said desired potential, and to provide a triggering signal to said rectifier gate to tire said detonator when said inverter circuit is in said first conduction state and said capacitor has been charged to said desired potential, appli whereby said rectifier is precluded from firing by the application of an erroneous triggering signal in the absence of the desired charge on said capacitor.

2. An electronic firing circuit as defined in claim 1 wherein said silicon controlled rectifier is a composite PNP/NPN bipolar transistor formed on a monolithic substrate using complementary symmetry MOS diffusion profiles.

3. An electronic firing circuit as defined in claim 2, wherein said first transistor of said charging circuit, said complementary pair of transistors of said inverter circuit, and said further transistors of said triggering means are MOS transistors formed on said same monolithic substrate.

4. In combination:

a capacitor for storing energy;

a load for utilizing said energy;

a first switch for applying a charging current to said capacitor in response to a first control signal for storing said energy in said capacitor;

a thyristor switch in a circuit for discharging said energy stored in said capacitor to said load in response to a second control signal;

another switch for inhibiting application of said second control signal to said thyristor switch when the charge on said capacitor is less than a given value so that the energy in said capacitor can be discharged into said load in response to said second control signal if and only if the first control signal is applied to said first switch for a length of time sufficient for said capacitor to be charged to said given value.

5. The combination recited in claim 4 wherein said thyristor switch is a silicon controlled rectifier (SCR) having a gate terminal for receiving said second control signal and having anode and cathode terminals, said load being connected in series with the anode to cathode current path of said SCR and the series connected SCR and load coupled in parallel with said capacitor so that energy stored in said capacitor is discharged into said load when the SCR gate is triggered in response to said second control signal.

6. The combination recited in claim 5 wherein said load is coupled between the SCR cathode and one terminal of said capacitor, the other terminal of said capacitor being coupled to said SCR anode.

7. The combination recited in claim 5 wherein said load is coupled between the SCR anode and one terminal of said capacitor, the other terminal of said capacitor being coupled to said SCR cathode.

8. The combination recited in claim 5 further including a circuit input terminal for receiving said second control signal and wherein said another switch is a transistor having a conduction path and a control electrode for controlling the conduction of the path, said control electrode being coupled to one terminal of said capacitor, and said conduction path providing coupling between said circuit input terminal and said gate terminal of said SCR.

9. The combination recited in claim 8 wherein said transistor is a field effect transistor.

10. The combination recited in claim 9 wherein said load is a current responsive explosive firing device.

11. In combination;

charge storage means;

means responsive to a first control signal for applying a charge to said charge storage means;

a first switch having a normally substantially open conduction path, a control electrode for controlling the condition of said path, an input terminal at one end of the path and an output terminal at the other end of the path, said control electrode being connected to said charge storage means and responsive to a charge stored therein of greater than a given value for substantially closing said path;

connections for a load;

a second switch having a substantially normally open circuit path connecting said charge storage means to said connections for said load and having a control electrode responsive to a second control signal for substantially closing said path, thereby permitting said charge storage means to discharge into said load connections, said control electrode being connected to the output terminal of said first switch; and

means for applying a second control signal to the input terminal of said first switch, whereby in the absence of a charge of greater than said given value in said charge storage means, said second control signal does not pass through said first switch and in the presence of such a charge, said second contr ol signal passes through said first switch and closes said second switch.

12. The combination recited in claim 11 wherein said second switch comprises a silicon controlled rectifier having a conduction path and a gate electrode for controlling the conduction of the path, said conduction path and said load connections being connected in series across said charge storage means, said gate electrode being connected to said output terminal of said first switch for receiving said second control signal.

13. The combination recited in claim 12 wherein said charge storage means comprises a capacitor and wherein said means responsive to a first control signal comprises a transistor, said transistor having a conduction path coupled between a circuit point for receiving a source of operating potential and one terminal of said capacitor, the other terminal of said capacitor being coupled to a circuit reference point, said transistor having a control electrode for controlling the conduction of the path in response to said first control signal.

14. The combination recited in claim 13 wherein said first switch comprises a field-effect transistor.

15. The combination recited in claim 14 wherein said load comprises a current responsive explosive firing device. 

1. An electronic firing circuit comprising: a silicon controlled rectifier having anode, cathode, and gate electrodes; detonating means adapted to fire an explosive charge, said detonating means being connected in series circuit with the anode-to-cathode path of said rectifier; a firing capacitor connected in circuit with said series combination, said capacitor being adapted to provide a firing current to said detonating means via said anode-to-cathode path; a charging circuit including a first transistor connected in circuit with said capacitor, said charging circuit being adapted to charge said capacitor to a desired potential upon the application of an arming signal to the control electrode of said transistor; an inverter circuit comprising a complementary pair of transistors and having an input terminal and an output terminal, said inverter circuit exhibiting a first conduction state in response to a given logic signal at its input terminal and a second conduction state in the absence of said given logic signal; logic means for generating said given logic signal, said logic means being connected to said inverter input; and triggering means including a further transistor connected in circuit with said inverter output terminal, said rectifier gate electrode and said capacitor; said triggering means being adapted to preclude the application of a triggering signal to said rectifier gate when the charge on said capacitor is below said desired potential, and to provide a triggering signal to said rectifier gate to fire said detonator when said inverter circuit is in said first conduction state and said capacitor has been charged to said desired potential, appli whereby said rectifier is precluded from firing by the application of an erroneous triggering signal in the absence of the desired charge on said capacitor.
 2. An electronic firing circuit as defined in claim 1 wherein said silicon controlled rectifier is a composite PNP/NPN bipolar transistor formed on a monolithic substrate using complementary symmetry MOS diffusion profiles.
 3. An electronic firing circuit as defined in claim 2, wherein said first transistor of said charging circuit, said complementary pair of transistors of said inverter circuit, and said further transistors of said triggering means are MOS transistors formed on said same monolithic substrate.
 4. In combination: a capacitor for storing energy; a load for utilizing said energy; a first switch for applying a charging current to said capacitor in response to a firSt control signal for storing said energy in said capacitor; a thyristor switch in a circuit for discharging said energy stored in said capacitor to said load in response to a second control signal; another switch for inhibiting application of said second control signal to said thyristor switch when the charge on said capacitor is less than a given value so that the energy in said capacitor can be discharged into said load in response to said second control signal if and only if the first control signal is applied to said first switch for a length of time sufficient for said capacitor to be charged to said given value.
 5. The combination recited in claim 4 wherein said thyristor switch is a silicon controlled rectifier (SCR) having a gate terminal for receiving said second control signal and having anode and cathode terminals, said load being connected in series with the anode to cathode current path of said SCR and the series connected SCR and load coupled in parallel with said capacitor so that energy stored in said capacitor is discharged into said load when the SCR gate is triggered in response to said second control signal.
 6. The combination recited in claim 5 wherein said load is coupled between the SCR cathode and one terminal of said capacitor, the other terminal of said capacitor being coupled to said SCR anode.
 7. The combination recited in claim 5 wherein said load is coupled between the SCR anode and one terminal of said capacitor, the other terminal of said capacitor being coupled to said SCR cathode.
 8. The combination recited in claim 5 further including a circuit input terminal for receiving said second control signal and wherein said another switch is a transistor having a conduction path and a control electrode for controlling the conduction of the path, said control electrode being coupled to one terminal of said capacitor, and said conduction path providing coupling between said circuit input terminal and said gate terminal of said SCR.
 9. The combination recited in claim 8 wherein said transistor is a field effect transistor.
 10. The combination recited in claim 9 wherein said load is a current responsive explosive firing device.
 11. In combination; charge storage means; means responsive to a first control signal for applying a charge to said charge storage means; a first switch having a normally substantially open conduction path, a control electrode for controlling the condition of said path, an input terminal at one end of the path and an output terminal at the other end of the path, said control electrode being connected to said charge storage means and responsive to a charge stored therein of greater than a given value for substantially closing said path; connections for a load; a second switch having a substantially normally open circuit path connecting said charge storage means to said connections for said load and having a control electrode responsive to a second control signal for substantially closing said path, thereby permitting said charge storage means to discharge into said load connections, said control electrode being connected to the output terminal of said first switch; and means for applying a second control signal to the input terminal of said first switch, whereby in the absence of a charge of greater than said given value in said charge storage means, said second control signal does not pass through said first switch and in the presence of such a charge, said second control signal passes through said first switch and closes said second switch.
 12. The combination recited in claim 11 wherein said second switch comprises a silicon controlled rectifier having a conduction path and a gate electrode for controlling the conduction of the path, said conduction path and said load connections being connected in series across said charge storage means, said gate electrode being connected to said output terminal of said first switch for receiving said second contRol signal.
 13. The combination recited in claim 12 wherein said charge storage means comprises a capacitor and wherein said means responsive to a first control signal comprises a transistor, said transistor having a conduction path coupled between a circuit point for receiving a source of operating potential and one terminal of said capacitor, the other terminal of said capacitor being coupled to a circuit reference point, said transistor having a control electrode for controlling the conduction of the path in response to said first control signal.
 14. The combination recited in claim 13 wherein said first switch comprises a field-effect transistor.
 15. The combination recited in claim 14 wherein said load comprises a current responsive explosive firing device. 